What Are Physical Register Files

Microprocessor Design

Registers are temporary storage locations inside the CPU that concord information and addresses.

The register file is the component that contains all the general purpose registers of the microprocessor. A few CPUs also place special registers such every bit the PC and the status register in the register file. Other CPUs keep them separate.

When designing a CPU, some people distinguish between "architectural features" and the "implementation details". The "architectural features" are the programmer visible parts; if someone makes a new arrangement where whatever of these parts are different from the sometime CPU, then suddenly all the old software won't work on the new CPU. The "implementation details" are the parts that, although we put even more time and effort into getting them to piece of work, one can make a new organization that has a different style of implementing them, and notwithstanding proceed software compatibility -- some programs may run a lilliputian faster, other programs may run a little slower, only they all produce the same results as on the earlier motorcar.

The programmer-visible register set has more bear on on software compatibility than any other part of the datapath, and perhaps more than any other part in the unabridged computer. The architectural features of the programmer-visible register set are the number of registers, the number of bits in each annals, and the logical arrangement of the registers. Assembly linguistic communication programmers similar to accept many registers. Early microprocessors had painfully few registers, limited past the expanse of the chip. Today, many chips have room for huge numbers of registers, then the number of programmer-registers is limited by other constraints: More programmer-visible registers requires bigger operand fields. More programmer-visible registers requires more than fourth dimension saving and restoring registers on an interrupt or context switch. Software compatibility requires keeping exactly the same number, size, and organization of programmer-visible registers. Associates language programmers like a "apartment" accost space, where the full address of any location in (virtual) memory fits in a single accost register. And so the amount of (virtual) retentiveness desired past an architect sets a minimum width to each address annals. ^[1]

The idea of "general registers" -- a group of registers, any one of which can, at different times, operate as a stack pointer, index annals, accumulator, programme counter, etc. was invented around 1971.^[2]

While registers can be implemented every bit a bank of flip-flop registers, SRAM-based full-custom register files use less area and ability.^{[3] [4]}

The overall performance of many unmarried-flake CPUs is limited by the speed of the read operation of the register file.^[3]

Register File [edit | edit source]

A simple register file is a set of registers and a decoder. The register file requires an address and a data input.

However, this elementary register file isn't useful in a modern processor design, considering there are some occasions when we don't want to write a new value to a register. Also, nosotros typically want to read two values at in one case and write ane value back in a single cycle. Consider the following equation:

${\displaystyle C=A+B}$

To perform this operation, we want to read two values from the register file, A and B. We also have ane result that we want to write back to the annals file when the functioning has completed. For cases where nosotros practice not want to write any value to the annals file, we add a control signal called Read/Write. When the control signal is high, the data is written to a register, and when the control bespeak is depression, no new values are written.

In this case, it is likely advantageous for us to specify a tertiary address port for the write address:

Many people choose to use a three-port register file for their pipelined microprocessor then information technology can execute such an ALU instructions every wheel. Every cycle the CPU reads values from ii registers in the register file to prepare for operating on them equally directed by ane instruction, and simultaneously the CPU writes the results from some previous teaching into some other register in the register file. (Superscalar Processors and VLIW require a annals file with 6 or more than ports).

(Does a microprocessor with operand forwarding ever read from a annals and write to the same register during the same clock wheel?)

Full-custom register files often start with a SRAM design. Like SRAM chips, SRAM-based register files include a differential pair of bit-lines for each port -- but instead of a single SRAM read/write port, register files typically have at least one dedicated write port and several defended read ports. A typical register file repeats this process every instruction cycle: Kickoff, the two bit-lines of a differential pair of each read port are shorted to each other and charged to Vdd/2 during a pre-charge phase. So the word-line connects one bit prison cell to those lines -- slightly imbalancing the charge on those long flake lines. Finally, the CPU enables the sense amplifier which magnifies the slight imbalance to normal digital logic levels.^{[5] [3] [6] [4]}

More than registers than y'all can milkshake a stick at [edit | edit source]

Consider a situation where the automobile give-and-take is very pocket-size, and therefore the bachelor accost infinite for registers is very limited. If nosotros have a machine word that can merely arrange two $.25 of register address, we can only address iv registers. However, annals files are small to implement, so we have enough space for 32 registers. There are several solutions to this dilemma -- several ways of increasing performance by using many registers, even though we don't quite take enough bits in the instruction discussion to directly address all of them.

Some of those solutions include:

• special-purpose registers that are always used for some specific instruction, and so that teaching doesn't need any bits to specify that register.
  • In well-nigh every CPU, the program counter PC and the status register are treated differently than the other registers, with their own special set of instructions.
• separating registers into two groups, "accost registers" and "information registers", so an instruction that uses an address needs plenty bits to select ane out of all the address registers, which is 1 less bit than 1 out of every annals.
• register windowing every bit on SPARC

^[1] and

• using a "annals bank".

To do: say a few words nearly "shadow registers"

To practise: say a few words about "register renaming"

Annals Bank [edit | edit source]

The term "register bank" is used in 2 dissimilar senses.^[7] Some CPUs have several different groups (or "banks") of registers, rather than 1 monolithic register file.

One kind of "register banking" is similar to (principal memory) depository financial institution switching. Considering this kind is visible to the associates linguistic communication programmer, in this chapter we'll call it "architectural banked registers". Other kinds of "register banking" allow a CPU to run exactly the aforementioned software as a single-bank implementation (invisible to the assembly linguistic communication programmer), then in in this chapter we'll call them "microarchitectural banked registers" -- these implementation options take various advantages over a monolithic register file implementation.

architectural banked registers [edit | edit source]

Consider a situation where the machine word is very small, and therefore the available address space for registers is very limited. If we have a machine word that can only suit 2 $.25 of annals address, we tin can but accost 4 registers. However, register files are small to implement, so nosotros have enough infinite for 32 registers. The solution to this dilemma is to utilize a register bank which consists of a series of register files combined together.

A register depository financial institution contains a number of register files or pages. Simply one page tin can be agile at a fourth dimension, and there are additional instructions added to the ISA to switch betwixt the available register pages. Information values tin but be written to and read from the currently active register folio, but instructions tin can exist to motility information from one page to another.

As tin be seen in this image, the gray box represents the electric current page, and the page can be moved up and downwards on the register depository financial institution.

If the register depository financial institution has N registers, and a page tin only show Yard registers (with N > M), we can address registers with two values, n and g respectively. We can define these values as:

${\displaystyle n=\log _{2}(N)}$

${\displaystyle m=\log _{2}(Chiliad)}$

In other words, due north and 1000 are the number of bits required to address Northward and K registers, respectively. We tin can suspension down the address into a single value every bit such:

Where p is the number of $.25 reserved to specify the current register page. As nosotros can come across from this graphic, the current register address is simply the concatenation of the folio accost and the register address.

microarchitectural banked registers [edit | edit source]

At that place are several techniques that divide upwards the physical registers into several concrete register files ("banks"), using control logic to make the CPU as a whole still software-compatible to other implementations of the same CPU architecture that merely use one monolithic register file. In mod high-functioning CPU, such techniques are used to build software-compatible CPUs that run at higher speed, utilize less ability, and crave less expanse than implementing the same CPU compages with a unmarried conventional multiported register file.^{[8] [9]}

Replicating the entire register file, as in the POWER2 and the Alpha 21264 and the Alpha 21464,^{[viii] [7]} is the simplest kind of microarchitectural register cyberbanking. These CPUs implemented their register file internally with ii copies of the entire (architectural) register file, and connect half the functional units to each copy. This requires each register file to take the same number of write ports equally a monolithic register file (since all writes are sent to *both* copies to keep them in sync), merely each annals file requires merely half the number of read ports as a monolithic register file.

References [edit | edit source]

1. ↑ ^{a b} "Figurer architecture: fundamentals and principles of estimator design" by Joseph D. Dumas 2006 page 111.
2. ↑ "general registers" were invented by C. Gordon Bell and Allen Newell equally they were working on their volume, Computer Structures: Readings and Examples (1971). -- Frederik Nebeker. "More Treasured Texts" article. "IEEE Spectrum" 2003 July.
3. ↑ ^{a b c} Larry R. Fenstermaker. "Current mode sense amplifiers applied to dual port register files past Larry R. Fenstermaker". 1998.
4. ↑ ^{a b} Akshay Vijayashekar and Hasan Ali. "Optimized Register File Implementation". quote: "The purpose of this thesis is to implement a full custom, low ability and area efficient annals file for an Atmel 32-bit microcontroller. ... The size of the annals file is 32 words of 32 bits each with 2 write ports and iv read ports."
5. ↑ Norman P. Jouppi and Jeffrey Y. F. Tang "A twenty-MIPS Sustained 32-chip CMOS Microprocessor with High Ratio of Sustained to Peak Performance". doi:10.1.1.85.988. 1989. Department "4.2. The Annals File Sense Amplifier". p. 10-12.
6. ↑ Robert Reese. "Register Files". 1999.
7. ↑ ^{a b} "What does banking mean when practical to registers?"
8. ↑ ^{a b} Jessica H. Tseng, and Krste Asanović. "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors". 2003.
9. ↑ Il Park, Michael D. Powell, and T. N. Vijaykumar. "Reducing Register Ports for Higher Speed and Lower Energy". 2002.

What Are Physical Register Files,

Source: https://en.wikibooks.org/wiki/Microprocessor_Design/Register_File

Posted by: broderickthroosed.blogspot.com

Share this post